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| DS1350Y/AB 4096k Nonvolatile SRAM with Battery Monitor www.dalsemi.com FEATURES 10 years minimum data retention in the absence of external power Data is automatically protected during power loss Power supply monitor resets processor when VCC power loss occurs and holds processor in reset during VCC ramp-up Battery monitor checks remaining capacity daily Read and write access times as fast as 70 ns Unlimited write cycle endurance Typical standby current 50 A Upgrade for 512k x 8 SRAM, EEPROM or Flash Lithium battery is electrically disconnected to retain freshness until power is applied for the first time Full 10% VCC operating range (DS1350Y) or optional 5% VCC operating range (DS1350AB) Optional industrial temperature range of -40C to +85C, designated IND New PowerCap Module (PCM) package - Directly surface-mountable module - Replaceable snap-on PowerCap provides lithium backup battery - Standardized pinout for all nonvolatile SRAM products - Detachment feature on PowerCap allows easy removal using a regular screwdriver PIN ASSIGNMENT BW A15 A16 RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 A18 A17 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 GND VBAT 34-Pin POWERCAP MODULE (PCM) (USES DS9034PC POWERCAP) PIN DESCRIPTION A0 - A18 DQ0 - DQ7 CE WE OE RST BW VCC GND NC - Address Inputs - Data In/Data Out - Chip Enable - Write Enable - Output Enable - Reset Output - Battery Warning - Power (+5V) - Ground - No Connect DESCRIPTION The DS1350 4096k Nonvolatile SRAMs are 4,194,304-bit, fully static, nonvolatile SRAMs organized as 524,288 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. Additionally, the DS1350 devices have dedicated circuitry for monitoring the status of VCC and the status of the internal lithium battery. DS1350 devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM module. The devices can be used in place of 512k x 8 SRAM, EEPROM or Flash components. 1 of 12 111999 DS1350Y/AB READ MODE The DS1350 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs (A0 -A18) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1350 devices execute a write cycle whenever the WE and CE signals are in the active (low) state after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled (CE and OE active) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1350AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1350Y provides full functional capability for VCC greater than 4.5 volts and write protects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write protect themselves, all inputs become "don't care," and all outputs become highimpedance. As VCC falls below approximately 2.7 volts, the power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 2.7 volts, the power switching circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1350AB and 4.5 volts for the DS1350Y. SYSTEM POWER MONITORING DS1350 devices have the ability to monitor the external VCC power supply. When an out-of-tolerance power supply condition is detected, the NV SRAMs warn a processor-based system of impending power failure by asserting RST . On power-up, RST is held active for 200 ms nominal to prevent system operation during power-on transients and to allow tREC to elapse. RST has an open drain output driver. BATTERY MONITORING The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1M=test resistor for one second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced. The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing resumes. BW has an open drain output driver. 2 of 12 DS1350Y/AB FRESHNESS SEAL Each DS1350 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for battery backup operation. PACKAGES The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1350 PCM device to be surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow soldering. After a DS1350 PCM is reflow soldered, a DS9034PC is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper attachment. DS1350 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for further information. 3 of 12 DS1350Y/AB ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -0.3V to +7.0V 0C to 70C, -40C to +85C for IND parts -40C to +70C, -40C to +85C for IND parts 260C for 10 seconds This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER DS1350AB Power Supply Voltage DS1350Y Power Supply Voltage Logic 1 Logic 0 SYMBOL VCC VCC VIH VIL MIN 4.75 4.5 2.2 0.0 TYP 5.0 5.0 MAX 5.25 5.5 VCC 0.8 (tA: See Note 10) UNITS V V V V NOTES DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current CE VIH VCC Output Current @ 2.4V Output Current @ 0.4V Standby Current CE =2.2V Standby Current CE =VCC-0.5V Operating Current Write Protection Voltage (DS1350AB) Write Protection Voltage (DS1350Y) (VCC=5V =5% for DS1350AB) (tA: See Note 10) (VCC=5V =10% for DS1350Y) SYMBOL IIL IIO IOH IOL ICCS1 ICCS2 ICCO1 VTP VTP 4.50 4.25 4.62 4.37 MIN -1.0 -1.0 -1.0 2.0 200 50 600 150 85 4.75 4.5 TYP MAX +1.0 +1.0 UNITS A A mA mA A A mA V V 14 14 NOTES CAPACITANCE PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN TYP 5 5 MAX 10 10 (tA=25C) UNITS pF pF NOTES 4 of 12 DS1350Y/AB AC ELECTRICAL CHARACTERISTICS (VCC=5V =5% for DS1350AB) (tA: See Note 10) (VCC=5V =10% for DS1350Y) DS1350AB-70 DS1350Y-70 DS1350AB-100 DS1330Y-100 MIN 100 MAX 100 50 100 5 25 5 70 55 0 5 12 25 5 30 0 7 5 40 0 7 5 100 75 0 5 12 35 35 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 12 13 5 5 4 12 13 3 5 5 NOTES PARAMETER Read Cycle Time Access Time OE CE OE SYMBOL tRC tACC tOE tCO tCOE tOD tOH tWC tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 MIN 70 MAX 70 35 70 to Output Valid to Output Valid or CE to Output Active 5 Output High Z from Deselection Output Hold from Address Change Write Cycle Time Write Pulse Width Address Setup Time Write Recovery Time Output High Z from WE Output Active from WE Data Setup Time Data Hold Time READ CYCLE SEE NOTE 1 5 of 12 DS1350Y/AB WRITE CYCLE 1 SEE NOTES 2, 3, 4, 6, 7, 8, and 12 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 6, 7, 8, and 13 6 of 12 DS1350Y/AB POWER-DOWN/POWER-UP CONDITION BATTERY WARNING DETECTION SEE NOTE 14 7 of 12 DS1350Y/AB POWER-DOWN/POWER-UP TIMING PARAMETER VCC Fail Detect to CE and WE Inactive VCC slew from VTP to 0V VCC Fail Detect to RST Active VCC slew from 0V to VTP VCC Valid to CE and WE Inactive VCC Valid to End of Write Protection VCC Valid to RST Inactive VCC Valid to BW Valid SYMBOL tPD tF tRPD tR tPU tREC tRPU tBPU 150 200 150 2 125 350 1 MIN 150 15 TYP MAX 1.5 (tA: See Note 10) UNITS s s s s ms ms ms s 14 14 14 NOTES 11 BATTERY WARNING TIMING PARAMETER Battery Test Cycle Battery Test Pulse Width Battery Test to BW Active SYMBOL tBTC tBTPW tBW MIN TYP 24 MAX 1 1 (tA: See Note 10) UNITS hr s s NOTES (tA=25C) PARAMETER Expected Data Retention Time SYMBOL tDR MIN 10 TYP MAX UNITS years NOTES 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a Read Cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high-impedance state. 3. tWP is specified as the logical AND of CE and WE . tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS are measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high-impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in high-impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high-impedance state during this period. 8 of 12 DS1350Y/AB 9. Each DS1230Y has a built-in switch that disconnects the lithium source until VCC is first applied by the user. The expected tDR is defined as accumulative time in the absence of VCC starting from the time power is first applied by the user. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0C to 70C. For industrial products (IND), this range is -40C to +85C. 11. In a power-down condition the voltage on any pin may not exceed the voltage on VCC. 12. tWR1 and tDH1 are measured from WE going high. 13. tWR2 and tDH2 are measured from CE going high. 14. RST and BW are open drain outputs and cannot source current. External pullup resistors should be connected to these pins for proper operation. Both pins will sink 10 mA. DC TEST CONDITIONS Outputs Open Cycle = 200 ns for operating current All voltages are referenced to ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0 - 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input pulse Rise and Fall Times: 5 ns ORDERING INFORMATION DS1350 TTP - SSS - III Operating Temperature Range blank: 0 to 70 IND: -40 to +85C Access Speed 70: 70 ns 100: 100 ns Package Type P: 34-pin PowerCap Module VCC Tolerance AB: 5% Y: 10% 9 of 12 DS1350Y/AB DS1350Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE PKG DIM A B C D E F G INCHES MIN 0.920 0.980 0.052 0.048 0.015 0.020 NOM 0.925 0.985 0.055 0.050 0.020 0.025 MAX 0.930 0.990 0.080 0.058 0.052 0.025 0.030 10 of 12 DS1350Y/AB DS1350Y/AB NONVOLATILE SRAM, 34-PIN POWERCAP MODULE WITH POWERCAP PKG DIM A B C D E F G INCHES MIN 0.920 0.955 0.240 0.052 0.048 0.015 0.020 NOM 0.925 0.960 0.245 0.055 0.050 0.020 0.025 MAX 0.930 0.965 0.250 0.058 0.052 0.025 0.030 ASSEMBLY AND USE Reflow soldering Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented label-side up (live-bug). Hand soldering and touch-up Do not touch soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove part, apply flux, heat pad until solder reflows, and use a solder wick. LPM replacement in a socket To replace a Low Profile Module in a 68-pin PLCC socket, attach a DS9034PC PowerCap to a module base then insert the complete module into the socket one row of leads at a time, pushing only on the corners of the cap. Never apply force to the center of the device. To remove from a socket, use a PLCC extraction tool and ensure that it does not hit or damage any of the module IC components. Do not use any other tool for extraction. 11 of 12 DS1350Y/AB RECOMMENDED POWERCAP MODULE LAND PATTERN PKG DIM A B C D E INCHES MIN NOM 1.050 0.826 0.050 0.030 0.112 MAX - RECOMMENDED POWERCAP MODULE SOLDER STENCIL PKG DIM A B C D E INCHES MIN NOM 1.050 0.890 0.050 0.030 0.080 MAX - 12 of 12 |
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